High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

This paper presents a low-latency hardware accelerator for modular polynomial multiplication lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce computational complexity of schoolbook multiplication. We also extend this structure $M$-parallel architectures while achieving low-latency, high-speed, full utilization. comprehensively evaluate performance under various settings as well in Saber scheme case study. experimental results show that our reduces computation time area-time product, respectively, compared state-of-the-art designs.